Book, 3rd Edition
Chapter 2: All Sections except for 2.5.1
Chapter 3: All Sections except for 3.4, 3.6.1 to 3.6.4, 3.7, 3.8, 3.9, 3.10
Chapter 4: All Sections except for 4.8, 4.9, 4.10
Chapter 5: All Sections except for 5.6, 5.7, Only Parity is needed in section 5.8
Chapter 6: All Sections
Chapter 7: All Sections except for 7.4.4, 7.12, 7.13, 7.14, 7.15 
Chapter 8: All Sections except for 8.4, 8.6, 8.8, 8.10

 

COE 328 Course Outline 

COE 328 Course Outline in ECBE webpage 

1                    Objectives

 

This course covers the basics of digital logic circuits and design. Through the basic understanding of Boolean algebra and number systems it introduces the student to the fundamentals of combinational logic design and then to sequential circuits (both synchronous and asynchronous). Memory systems are also covered. Finally, the student is introduced to Register Transfer Logic design and the structured implementation of controllers and microprogrammed computers.

Technological constraints such as loading factors, noise margins, and various logic families are also introduced. Modern programmable devices (PLDs) including ROMs, CPLDs and FPGAs, as well as appropriate computer aided design (CAD) tools are also covered. There is an introduction to VHDL. Students will be provided with an opportunity to implement the PLD-based designs (using both schematic capture and VHDL) in actual chips.

By the end of the course the student will be able to design, simulate, build, and debug complex combinational and sequential digital circuits based on an abstract functional specification. The student will also understand the basic internal workings of the central processing unit of a computer and its interface with memory and input/output subsystems. The course gives students sufficient preparation for the third year microprocessor system course where small microprocessor systems are explored in depth at both hardware and software levels.

 

2                    2          Course Materials

 

Textbook:

 

Brown, S. and Vranesic, Z. Fundamentals of Digital Logic with VHDL Design, Third Edition, McGraw-Hill, 2009. ISBN 9780077272418.

 

Laboratory Manual:

 

Available through the course web page:  http://www.ee.ryerson.ca/~courses/coe328

 

References: (on reserve in the library)

 

Hayes, J. Introduction to Digital Logic Design, Addison Wesley, 1993. (Library call number TK7868.L6H29 1993).

Wakerly, J. Digital Design: Principles and Practices, Prentice Hall, 2003. (Library call number TK7874.65.W34 2000).

Dewey, A. Analysis and Design of Digital Systems with VHDL, PWS Publishing Company, 1997. (Library call number TK7868D5D47 1997).

 

 

3          Marking Scheme

The following table summarizes the marking scheme for the course.

 

 Note: In order for a student to pass a course with "Theory and Laboratory" components, in addition to earning a minimum overall course mark of 50%, the student must pass the Laboratory and Theory portions separately by achieving a minimum of 50% in the combined Laboratory components and 50% in the combined Theorycomponents. Please refer to the "Course Evaluation" section for details on the Theory and Laboratory  components.

 

4          Course Outline

The following table summarizes the lecture and laboratory topics and course schedule. Numbers next to topics refer to the section numbers in Brown and Vranesic or Hayes that cover the topic. Some material will be supplemented with handouts.

 

Note: For Fall term Labs begin in the second week.

 

LECTURE	LABORATORY
INTRODUCTION TO COE328   Scope and objectives Management   INTRODUCTION TO LOGIC CIRCUITS   2.1 Variables and Functions 2.2 Inversion 2.3 Truth tables 2.4 Logic gates and networks 2.5 Boolean Algebra
INTRODUCTION TO LOGIC CIRCUITS   2.6 Synthesis Using AND, OR, and NOT Gates 2.7 NAND & NOR Logic Networks 2.8 Design Examples 2.9 Introduction to CAD tools 2.10 Introduction to VHDL   IMPLEMENTATION TECHNOLOGY   3.1 Transistor switches 3.2, 3.3 NMOS and CMOS Logic Gates 3.5 Standard Chips 3.6 Programmable Logic Devices	Lab 1: Introduction to CAD Tools  (2 weeks)
IMPLEMENTATION TECHNOLOGY   3.7 Custom Chips, Standard Cells, and Gate Arrays 3.8 Practical Aspects 3.9 Transmission Gates 3.10 Implementation Details for CPLDs and FPGAs   OPTIMIZATION OF COMBINATIONAL LOGIC   4.2 Strategy for Minimization (Sum-of-Products Forms) ¡P  4.3 Minimization of Product-of-Sums Forms ¡P  4.4 Incompletely specified functions ¡P  4.5 Multiple-Output Circuits ¡P  4.6 Multilevel Synthesis ¡P  4.7 Analysis of Multilevel Circuits ¡P  4.12 Examples of Circuits Synthesized from VHDL code
NUMBER REPRESENTATION AND ARITHMETIC CIRCUITS   5.1 Positional Number Representation 5.2 Addition of Unsigned Numbers 5.3 Signed Numbers 5.4 Fast Adders 5.5 Design of Arithmetic Circuits Using CAD 5.7 Other Number Representations 5.8 ASCII Character Code	Lab 2: Function Implementation and Minimization (1 week)
COMBINATIONAL CIRCUIT BUILDING BLOCKS   6.1 Multiplexers 6.2 Decoders 6.3 Encoders 6.4 Code Converters 6.5 Arithmetic Comparison Circuits 6.6 VHDL for Combinational Circuits	Lab 3: Adder and Substractor Unit (2 weeks)
INTRODUCTION TO SEQUENTIAL CIRCUITS   7.1 Basic Latch 7.2 Gated SR-Latch 7.3 Gated D Latch 7.4 Master-Slave and Edge-Triggered D Flip-Flops 7.5 T Flip-Flop 7.6 JK Flip-Flop 7.7 Summary of Terminology
INTRODUCTION TO SEQUENTIAL CIRCUITS   7.8 Registers 7.9 Counters   MIDTERM TEST	Lab 4: ) VHDL for Combinational Circuits and Storage Elements (2 week)

 

LECTURE	LABORATORY
INTRODUCTION TO SEQUENTIAL CIRCUITS   7.10 Reset Synchronization 7.11 Other Types of Counters 7.12 Using Storage Elements with CAD Tools 7.13 Using Registers and Counters with CAD Tools   SYNCHRONOUS SEQUENTIAL CIRCUITS   8.1 Basic Design Steps 8.2 State Assignment Problem
SYNCHRONOUS SEQUENTIAL CIRCUITS   8.3 Mealy State Model 8.4 Design of Finite State Machine Using CAD Tools 8.6 State Minimization 8.7 Design of Counter Using the Sequential Circuit Approach 8.9 Analysis of Synchronous Sequential Circuits   REGISTER-LEVEL DESIGN   8.1 General Characteristics [Hayes, pp. 599-605, 609-611,613] 8.4 ¡V 8.6 Datapath and Control Units [Hayes, 636-642, 652-654, 668-673]	Lab 5: VHDL for Sequential Circuits: Implementing an Eight-State Machine (2 week)
SYSTEM ARCHITECTURE   9.1 Basic System Architecture [Hayes, 715-721] Lab 6 (Project) Discussion

 

SYSTEM ARCHITECTURE   9.2 ¡V 9.3 CPU, Memory, and Input/Output [Hayes, 721-737] 9.4 CPU Operation [Hayes, 740-754]   Faculty/Course Evaluation	Lab 6: Design of a Simple General Purpose Processor (3 week)
ASYNCHRONOUS SEQUENTIAL CIRCUITS   9.1 Asynchronous Behavior 9.2, 9.3 Analysis and Synthesis of Asynchronous Circuits 9.6 Hazards
REVIEW	Lab 6 Report
FINAL EXAMINATION

 

5          Lab Management

 

Credit for labs will be based on the quality of pre-lab preparation, how the Lab works (demonstration) and how well the student can answer questions about the lab. Labs where pre-lab preparation is inadequate will be marked as 0, although the student will be given an opportunity to rectify his or her preparation. Partial marks may be assigned at the discretion of the instructor.

.

Each student must also keep a complete and continuous record in a binder of the year¡¦s lab activities.

Labs are done in groups by 2 students or individually.

            Equipment should not be moved during the lab; if you believe equipment to be defective, report it to the lab instructor who will take care of the problem.

 

 

Marking Scheme & Schedule for Lab Work 

 

Week	Labs
1
2	#1   (10 marks) Introduction to CAD Tools
3	#1   (10 marks) Introduction to CAD Tools
4	#2   (10 marks) Functional Implementation &Minimization
5	#3  (15 marks) Adder and Subtractor Unit
6	#3  (15 marks) Adder and Subtractor Unit
7	#4 (15 marks) VHDL for Combinational Circuits and Storage Elements
8	#4 (15 marks) VHDL for Combinational Circuits and Storage Elements
9	#5 (15 marks) VHDL for Sequential Circuits: Implementing an Eight-State Machine
10	#5 (15 marks) VHDL for Sequential Circuits: Implementing an Eight-State Machine
11	#6 (35 marks) Design of a Simple General Purpose Processor
12	#6 (35 marks) Design of a Simple General Purpose Processor
13