| Instructor(s) | Dr. Andy Ye [Coordinator] Office: ENG319 Phone: (416) 979-5000 x 554901 Email: agye@torontomu.ca Office Hours: Tuesdays 4:00pm to 5:00pm | ||||||||||||||||||
| Calendar Description | This course deals with the design of Digital CMOS integrated circuits. The course consists of three essential components: Theory, Laboratory, and project. Variety of design techniques, such as Static CMOS, Dynamic CMOS, and Transmission Gate are discussed in theory. These designs are studied on basic logic gates as well as combinational and sequential circuits. The lessons learned are applied to arithmetic building blocks such as adders and decoders. A MOS transistor is studied using I-V equations, and the different areas of operations are modeled. The static (DC) are dynamic (transient) behaviors for an important building block, a CMOS inverter, are studied in depth. | ||||||||||||||||||
| Prerequisites | COE 538 | ||||||||||||||||||
| Antirequisites | None | ||||||||||||||||||
| Corerequisites | None | ||||||||||||||||||
| Compulsory Text(s): |
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| Reference Text(s): | |||||||||||||||||||
| Learning Objectives (Indicators) | At the end of this course, the successful student will be able to:
NOTE:Numbers in parentheses refer to the graduate attributes required by the Canadian Engineering Accreditation Board (CEAB). | ||||||||||||||||||
| Course Organization | 3.0 hours of lecture per week for 13 weeks | ||||||||||||||||||
| Teaching Assistants | TBA | ||||||||||||||||||
| Course Evaluation |
Note: In order for a student to pass a course, a minimum overall course mark of 50% must be obtained. In addition, for courses that have both "Theory and Laboratory" components, the student must pass the Laboratory and Theory portions separately by achieving a minimum of 50% in the combined Laboratory components and 50% in the combined Theory components. Please refer to the "Course Evaluation" section above for details on the Theory and Laboratory components (if applicable). | ||||||||||||||||||
| Examinations | Midterm exam in Week 9, 1.5 hours, closed book (covers Weeks 1-6 of lecture and laboratory material). Final exam, during exam period, 3 hours, closed book (covers all the course material). | ||||||||||||||||||
| Other Evaluation Information | * The mid-term test and final examination will be closed book. * In order to achieve a passing grade in this course, the student must achieve an average of at least 50% in both theoretical and laboratory components. * The written reports will be assessed not only on their technical or academic merit, but also on the communication skills of the author as exhibited through the reports. | ||||||||||||||||||
| Teaching Methods | In person Lectures and Labs. | ||||||||||||||||||
| Other Information | 7 Lab/tutorial sections of maximum 25 students each 2 Teaching Assistants, 3-4 sections per TA | ||||||||||||||||||
Week | Hours | Chapters / | Topic, description |
|---|---|---|---|
1 (Sep 14-20) | 3 | 1 | Chapter 1- Introduction (Sections 1.1, 1.3, 1.4, 1.5) |
2 (Sep 21-27) | 3 | 1 & 2 | Chapter 1- Introduction (Section 1.5) |
3 (Sep 28-4) | 3 | 2 | Chapter 2- MOS Transistor Theory (Sections 2.5, 2.3, 2.4) |
4 (Oct 5-11) | 3 | 4 | Chapter 4- Delay (4.1, 4.2, 4.3, 4.4) |
5 (Oct 12-18) | 3 | Week of Thanksgiving Monday: No Class | |
6 (Oct 19-25) | 3 | 4 & 5 | Chapter 4- Delay (4.5) |
7 (Oct 26-1) | 3 | 5 | Chapter 5- Power (5.2, 5.3) |
8 (Nov 2-8) | 3 | 5 & 6 | Chapter 5- Power (5.3) |
9 (Nov 9-15) | 3 | Midterm on November 6th during class hours | |
10 (Nov 16-22) | 3 | 6, 8, 9 | Chapter 6- Interconnect (6.4) |
11 (Nov 23-29) | 3 | 9 | Chapter 9- Combinational Circuit Design (9.2) |
12 (Nov 30-6) | 3 | 11 | Chapter 11- Datapath Subsystems (11.1, 11.2) |
13 (Dec 7) | 3 | 11 & 10 | Babbage Difference Engine Carry Skip Adder |
Week | L/T/A | Description |
|---|---|---|
2-4 | ENG412 | Characteristics of MOSFET Devices |
5-6 | ENG412 | CMOS Inverter Design |
7-9 | ENG412 | CMOS Logic Families |
10-12 | ENG412 | 1-bit CMOS Full Adder |
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Refer to the Departmental FAQ page for furhter information on common questions.
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For Extenuating Circumstances, Policy 167: Academic Consideration allows for a once per semester ACR request without supporting documentation if the absence is less than 3 days in duration and is not for a final exam/final assessment. Absences more than 3 days in duration and those that involve a final exam/final assessment, always require documentation. Students must notify their faculty/contract lecturer once a request for academic consideration is submitted. See Senate Policy 167: Academic Consideration.
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If you have (or suspect you may have) a disability, AAS can provide consultation, guide you through registration, develop accommodation plans where appropriate, and connect you with supports and services. For information about eligibility, documentation requirements, registration, deadlines, and available services, visit AAS.
Academic Accommodations (for students with disabilities) and Academic Consideration (for short-term extenuating circumstances) are governed by different university policies. Learn more about each process and how to access support. Students registered with AAS may request academic consideration (related or unrelated to their disability) if they experience extenuating circumstances that impact their ability to meet their shorter term academic obligations. This includes short term physical or mental health issues that are sudden/acute (e.g, the flu), unexpected illness or injury, hospitalization or treatment, and significant aggravation of a pre-existing condition. Please see Policy 167: Academic Consideration for more information and details.
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